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IEEE Transactions on Very Large Scale Integration Systems

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems  covers design and realization of microelectronic systems using VLSI/ULSI technologies that require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following:

• System Specification, Design and Partitioning
• System-level Test
• Reliable VLSI/ULSI Systems
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• Wafer Scale Integration and Multichip Modules (MCMs)
• High-Speed Interconnects in Microelectronic Systems
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IEEE Transactions on Very Large Scale Integration Systems (TVLSI) Editorial Board

Editor-in-chief, mircea r. stan, associate editor-in-chief, associate editor tvlsi, magdy abadir, tughrul arslan, amine bermak, chye chirin boon, andreas burg, chip hong chang, meng-fan (marvin) chang, yao-wen chang, yong (nick) chen, paolo s. crovetti, josé pineda de gyvez, raffaele de rose, shiro dosho, rolf drechsler, ibrahim (abe) elfadel, xuanyao (kelvin) fong, masanori hashimoto, deukhyoun heo, tsung-yi ho, houman homayoun, yuh-shyan hwang, rajiv joshi, tanay karnik, tony tae-hyoung kim, chulwoo kim, seok-bum ko, jaydeep kulkarni, volkan kursun, yoonmyung lee, hai (helen) li, longyang lin, prabhat mishra, baker mohammad, mehran mozaffari kermani, makoto nagata, mahdi nikdast, partha p pande, bipul c. paul, vasilis pavlidis, khaled n salama, patrick schaumont, fabio sebastiano, anirban sengupta, mingoo seok, vaishnav srinivas, ioannis l. syllaios, armin tajalli, mark tehranipoor, aida todri-sanial, marian verhelst, valerio vignoli, xiaoqing wen, kaiyuan yang, zhengya zhang, mark zwolinski, editorial assistant, stacey weber jackson.

VLSI-SoC: Design Trends

28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers

• Conference proceedings
• © 2021
• Andrea Calimera   ORCID: https://orcid.org/0000-0001-5881-3811 0 ,
• Pierre-Emmanuel Gaillardon   ORCID: https://orcid.org/0000-0003-3634-3999 1 ,
• Kunal Korgaonkar   ORCID: https://orcid.org/0000-0002-9078-2944 2 ,
• Shahar Kvatinsky   ORCID: https://orcid.org/0000-0001-7277-7271 3 ,
• Ricardo Reis   ORCID: https://orcid.org/0000-0001-5781-5858 4

Politecnico di Torino, Turin, Italy

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University of Utah, Salt Lake City, USA

Technion – israel institute of technology, haifa, israel, universidade federal do rio grande do sul, porto alegre, brazil.

Part of the book series: IFIP Advances in Information and Communication Technology (IFIPAICT, volume 621)

Included in the following conference series:

• VLSI-SoC: IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip

Conference proceedings info: VLSI-SoC 2020.

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About this book

The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs.

*The conference was held virtually.

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Very Large Scale Integration (VLSI) and ASICs

VLSI-SoC: An Enduring Tradition

ITRS 2028—International Roadmap of Semiconductors

• artificial intelligence
• communication systems
• computer hardware
• computer-aided design
• distributed computer systems
• distributed systems
• embedded systems
• field programmable gate array
• integrated circuits
• microprocessor chips
• network protocols
• parallel processing systems
• signal processing
• telecommunication systems
• vlsi circuits

Table of contents (16 papers)

Front matter, low-power high-speed adcs for adc-based wireline receivers in 22 nm fdsoi.

• David Cordova, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, Nicolas Nodenot et al.

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

• Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli

Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring

• Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

• Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta et al.

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform

• Alessandro Veronesi, Davide Bertozzi, Milos Krstic

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays

• Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek

Learning Based Timing Closure on Relative Timed Design

• Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication

• Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury

From Informal Specifications to an ABV Framework for Industrial Firmware Verification

• Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli

Modular Functional Testing: Targeting the Small Embedded Memories in GPUs

• Josie Esteban Rodriguez Condia, Matteo Sonza Reorda

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique

• Jonas Gava, Ricardo Reis, Luciano Ost

SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption

• Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo

3D Nanofabric : Layout Challenges and Solutions for Ultra-scaled Logic Designs

• Edouard Giacomin, Juergen Boemmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

• Arnaud Poittevin, Chhandak Mukherjee, Ian O’Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng et al.

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics

• Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung-Kyu Lim, Arijit Raychowdhury

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory

• Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatinsky

Back Matter

Other volumes, editors and affiliations.

Andrea Calimera

Pierre-Emmanuel Gaillardon

Kunal Korgaonkar, Shahar Kvatinsky

Ricardo Reis

Bibliographic Information

Book Title : VLSI-SoC: Design Trends

Book Subtitle : 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers

Editors : Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis

Series Title : IFIP Advances in Information and Communication Technology

DOI : https://doi.org/10.1007/978-3-030-81641-4

Publisher : Springer Cham

eBook Packages : Computer Science , Computer Science (R0)

Copyright Information : IFIP International Federation for Information Processing 2021

Hardcover ISBN : 978-3-030-81640-7 Published: 15 July 2021

Softcover ISBN : 978-3-030-81643-8 Published: 15 July 2022

eBook ISBN : 978-3-030-81641-4 Published: 14 July 2021

Series ISSN : 1868-4238

Series E-ISSN : 1868-422X

Edition Number : 1

Number of Pages : XVIII, 364

Number of Illustrations : 70 b/w illustrations, 139 illustrations in colour

Topics : Computer Systems Organization and Communication Networks , Control Structures and Microprogramming , Input/Output and Data Communications , Information Systems Applications (incl. Internet)

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VLSI Architectures for Wireless Communications and Digital Signal Processing

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• Published Papers

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section " Circuit and Signal Processing ".

Deadline for manuscript submissions: closed (31 August 2022) | Viewed by 16865

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Dear Colleagues,

Due to the relentless growth of computational complexity, state-of-the-art technologies cannot be realized unless they are accelerated by very-large-scale-integration (VLSI) circuits. For instance, 5G telecommunications necessitate application-specific integrated circuits (ASICs) to achieve data rates over tens of gigabits per second. The Internet-of-Things (IoT) systems connecting a massive number of edge devices also demand highly efficient hardware to accommodate data transfer within a few milliseconds under a limited power budget. Computer-vision applications based on deep neural networks are so computationally intensive that they incur orders-of-magnitude more operations than ever before. To facilitate the realization of such cutting-edge technologies, considerable attention should be paid to the development of efficient VLSI architectures.

This Special Issue solicits original and unpublished papers on high-performance and low-power VLSI architectures and the relevant algorithmic optimizations in the field of wireless communications and digital signal processing.

The topics of interest include but are not limited to:

• VLSI architectures for 5G and 6G telecommunications;
• FPGA and ASIC implementations of signal-processing systems;
• Baseband signal processing for communication systems;
• Circuits and systems for the Internet-of-Things (IoT);
• VLSI architectures for machine learning and artificial intelligence;
• Application-specific instruction-set processors for digital signal processing;
• Hardware-friendly algorithms and optimization techniques;
• Embedded systems on chip (SoCs) for signal-processing applications.

Prof. Dr. Byeong Yong Kong Prof. Dr. Hoyoung Yoo Guest Editors

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website . Once you are registered, click here to go to the submission form . Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

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UVA’s Mircea Stan and ECE’s Wayne Burleson Ace the “Test of Time” with their IEEE Technical Impact Award

The Institute of Electrical and Electronics Engineers (IEEE) has selected Professor Mircea Stan of the University of Virginia (UVA) and his former mentor at UMass Amherst, Professor of Electrical and Computer Engineering (ECE) Wayne Burleson, to receive the 2024  A. Richard Newton Technical Impact Award in Electronic Design Automation for their 1995 paper based on Stan’s research. According to the IEEE, the award was established “to honor a person or persons for an outstanding technical contribution within the scope of electronic-design automation, as evidenced by a paper published at least 10 years before the presentation of the award.” The winning paper – published in the March 1, 1995, issue of  IEEE Transactions on Very Large Scale Integration Systems – was titled  Bus-invert Coding for Low-Power I/O .

Stan and Burleson’s pioneering 1995 paper offered an elegant solution to the troublesome issue of inefficient power dissipation in the input/output (I/O) of an integrated circuit.

In their 1995 paper, Stan and Burleson suggested a visionary proposal: “the bus-invert method of coding the I/O, which lowers the bus activity and thus decreases the I/O peak power dissipation by 50 percent and the I/O average power dissipation by up to 25 percent.” 

Stan and Burleson added that “The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power.”

As Stan and Burleson explained the backstory to their paper, “Technology trends and especially portable applications drive the quest for low-power, very-large-scale-integration (VLSI) design. Solutions that involve algorithmic, structural, or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period).” 

Stan and Burleson went on to say that “For complementary metal-oxide-semiconductor (CMOS) circuits, most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit.” 

According to Stan and Burleson, “While it is generally accepted that (because of the large capacitances involved) much of the power dissipated by an integrated circuit is at the I/O, little has been specifically done for decreasing the I/O power dissipation.” Their 1995 paper tackled that specific problem in what has proven to be a groundbreaking way over the past three decades.

Stan is currently the director of the UVA School of Engineering and Applied Science’s Computer Engineering Program and director of the Computer Engineering Virginia Microelectronics Consortium. He received his diploma degree from the Politehnica University of Bucharest in Romania in 1984 and later earned his M.S. and Ph.D. degrees from UMass Amherst in 1994 and 1996, respectively. He teaches in the UVA Department of Electronics and Communication Engineering and does research in high-performance, low-power VLSI, temperature-aware circuits and architecture, embedded systems, and nanoelectronics.

Stan is a member of the Association for Computing Machinery, Eta Kappa Nu, Phi Kappa Phi, and Sigma Xi. He was a recipient of the National Science Foundation CAREER Award in 1997. He was also an associate editor of the IEEE Transactions on Circuits and Systems—Part I: Regular Papers from 2004 to 2008 and the IEEE Transactions on Very Large-scale Integration Systems from 2001 to 2003. Currently, he is an associate editor of the IEEE Transactions on Nanotechnology . He was a Distinguished Lecturer of the IEEE Circuits and Systems Society from 2004 to 2005 and from 2012 to 2013.

Burleson has been in the ECE department at UMass Amherst since 1990. From 2012-2017, he was a Senior Fellow at AMD Research on a team whose research led to the most powerful and green supercomputers in the world. He has also had previous sabbaticals at EPFL, LIRM Montpellier, and Telecom Paris. 

Burleson has also worked as a custom-chip designer and consultant in the semiconductor industry with VLSI Technology, DEC, Compaq/HP, Intel, Rambus, and AMD, as well as several start-ups. His research is in the general area of security engineering and VLSI, including medical devices, radio-frequency identification, lightweight security, post-CMOS circuits, and computer-aided design for low-power, interconnects, clocking, reliability, thermal effects, process variation, and noise mitigation. 

Burleson has published more than 200 papers in refereed publications in these areas and is a Fellow of the IEEE for contributions to integrated-circuit design and signal processing. He has electrical-engineering degrees from the Massachusetts Institute of Technology and the University of Colorado. (June 2024)

Wayne Burleson

I develop integrated circuit hardware and software solutions for secure applications, including medical devices, transportation, payments and defense.

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